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Program
FINAL PROGRAM
The final SPI program is available here.
Sponsor Information may be further updated. The program of the IBIS meeting will be added when available.
Instructions for presenters (oral and poster) are available here.
SPI2018 HIGHLIGHTS
Tutorials - Tuesday, May 22nd 2018 14:00-17:30
Dr. Gianni Signorini, Intel Corporation, Germany Prof. Stefano Grivet-Talocia, Politecnico di Torino, Italy
Abstract. This tutorial will cover technological, architectural, modeling and simulation challenges for the Signal and Power Integrity of high-end mobile platforms. On one hand, the latest packaging technologies for mobile applications will be discussed, emphasizing their pros and cons in view of current and expected future system requirements. On the other hand, the architectural challenges will be translated into modeling and simulation challenges, that engineers have to face in their daily work for ensuring system-level signal and power quality. Fast simulation approaches based on reduced-order behavioral models for both interconnects and devices will be discussed in detail. Finally, case studies from real mobile applications will be illustrated.
Keynote Speech - Wednesday, May 23rd 2018 9:00-10:00
Unsung Heroes of Scaling – Interconnects in Sub-Nanometer Regime
Dr. Aida Todri-Sanial, CNRS, France
Abstract. Improving only the transistor performance of the future chip isn’t sufficient. Chips, of course, are only one small part of the very large and complex information technology puzzle, albeit a very important one. Thus, to shape the future of the digital world, we also have to look at the bigger picture. Transistors are only as good as the system in which they are embedded. Interconnects play an important role as the operation frequency of today’s CPUs is already governed by interconnect delays, and, during operation, most their power is dissipated in the interconnects. This is where current electrical copper (Cu) interconnects will approach their physical limitations and may no longer be able to keep pace with a processor’s data throughput. Besides, accelerated technology scaling has aggravated Cu resistivity increase due to electron scattering and even more severely, it introduced electromigration issues. Mass transport along interfaces and grain boundaries in state-of-the-art Cu interconnects is one of the most important issues to be solved for future technology nodes according to the International Roadmap of Semiconductors (ITRS). The research and development on Cu interconnect manufacturing have been carried out for over twenty years. Academics and industry expect view that the replacement of Cu metal for the finest metal tracks might occur in the next 1-3 scaling nodes. This keynote speech will focus on the impact of interconnects on circuits’ reliability, power-thermal-signal integrity, and overall energy efficiency. I will discuss why are switching energy of current systems is far from the SNL limit and the role of interconnects. Then, I will provide an overview of novel interconnects materials architectures that have the potential to address the energy efficiency challenge. I will also discuss the three-dimensional integration as a novel design paradigm for integrating more functionality and heterogeneous systems while improving energy efficiency.
Interactive Industrial Forum - Thursday, May 24th 2018
The SPI Industry Forum is reaching its third edition and due to its success it is acquiring the status of an “event within the event”. The objective of this special session is to present and discuss problems rather than solutions, for those aspects of Signal and Power Integrity (and related topics) that have no good solution yet, neither theoretical, nor in form of EDA tools. The explicit goal is to foster the discussion between industry, academia, and tool vendors, so that the three communities can cooperate in the future and focus on the most relevant problems. This edition’s Industry Forum will feature talks from Michael W. Leddige (Intel, USA), Benoit Goral (Thales, France), Hubert Harrer (IBM Germany), Olivier Bayet (STMicroelectronics, France), Gianni Signorini (Intel Corporation, Germany).
Below you will find the slides of some presentations
Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net (slides)
A. Tsuchiya1, A. Hiratsuka (student)2, T. Inoue1, K. Kishine1, H. Onodera2
1Dept. Electronic Systems Engineering The University of Shiga Prefecture Hikone, Japan ; 2Dept. Communications and Computer Engineering Kyoto University Kyoto, Japan.
Modelling and Validation of High-Current Surface-Mount Current-Sense Resistor (slides)
J. Bačmaga (student)1, R. Blečić2, R. Gillon3, A. Barić1
1University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia; 2 KU Leuven, ESAT-TELEMIC, Leuven, Belgium; 3ON Semiconductor, Westerring Oudenaarde, Belgium
Power integrity of networking processor at system level (slides)
Olivier Bayet
STMicroelectronics, France
A Fully 3-D BIE Evaluation of the Resistance and Inductance of On-Board and On-Chip Interconnects (slides)
M. Huynen (student), D. De Zutter, and D. Vande Ginste
Electromagnetics Group/IDLab, Department of Information Technology, Ghent University/Imec, Gent, Belgium
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